Reducing Capacitive Coupling To Substrate
On a bulk CMOS process, substrate is the most important conductor on the chip as it is the one conductor that is common to everything. Keeping substrate as quiet as possible is key to ensuring that different functional circuits on the same die do not interfere with each other.
There are 3 primary ways that noise couples into substrate:
Understanding each of these coupling processes and putting a methodology in place to reduce the magnitude of this coupling is key to reducing substrate noise.How to Reduce Capacitive Coupling.
Route signals on higher metals
Very often top metals are reserved for power routing because they’re thicker and wider so offer a lower sheet resistance.This reduces any potential IR drop in supplies. Reserving top metals for power routing is also convenient in that routing can be placed over blocks at a late stage. But these are DC signals where capacitance is largely irrelevant, so lower level metals could be used instead. This reserves higher (if not the top) metal layers for signal routing.
Consider sharing and folding devices
Folding devices reduces a devices areaand reduces its capacitance to substrate. Similarly sharing between multiple devices has the same effect. Whilst both sharing and folding impact the device characteristics, which needs to be considered, these two steps can significantly reduce capacitive coupling to substrate.
Change Shape & Size of Passive Devices
A resistor of width 2u and length 10u has the exact same resistance as a resistor of width 1u and length 5u, but is 4 times the area, so almost 4 times the capacitance. The smaller area resistor may have issues relating to current density and/or accuracy/matching which again need to be considered, but from a capacitance point of view, the smaller area offers significant savings.
Changing the shape of the device can also potentially offer area savings, which feed directly into capacitance savings, particularly when dealing with capacitors. The perimeter area of a capacitor is a key factor in the overall capacitance. . A conductor plate of 7μ x 7μ has an overall area of 49μ2 and a perimeter area of 28μ. Changing the shape of this to 49μ x 1μ still maintains the overall area of 49μ2 but more than triples its perimeter to 100μ. This could potentially afford the layout engineer to reduce the actual area of the capacitor, whilst maintaining its original capacitance value.
Reduce the use of NMOS Devices
In the case of using a MOS device for power and ground decoupling, the NMOS and PMOS are directly interchangeable. As NMOS devices are more parasitic due to the fact they sit directly in substrate, layout engineers should instead consider using PMOS devices (assuming the Nwell is connected to a quiet supply)
Shield Routing Channels
Rather than routing signals over blank areas of substrate, opt instead to shield these channels. A conductor like Nwell, tied to a quiet supply would be a suitable shield. Other options like using implant block under channels should also be considered.
Shield Passive Devices
As with routing channels, passive devices should also be shielded from substrate where possible. Again Nwell would be a good choice, or implant block where possible.
Do Not Fill Blank Areas Of Die With PTAP
Field oxide is a thick oxide layer, deliberately grown thick to reduce capacitive coupling of conductors to substrate. It is the primary tool the foundry offers the layout engineer, in helping to keep substrate as clean as possibly from capacitively coupled noise.
Anytime a layout engineer opts to add PTAP connections, they remove this oxide, add a heavily doped P diffusion region (likely to be salicided) and worse still, add contacts and metal, bringing substrate much closer to adjacent conductors.
PTAP connections are required in close proximity to N junctions, but should be used very sparingly and with due consideration in all other cases.
These 6 simple intuitive steps, come with little or no cost in terms of time or area and yet offer significant reductions on substrate coupling, so are worth considering during the layout of all circuits.
This content is discussed in greater detail in IC Mask Designs Analog Layout, Advanced Techniques course (AALT) and RF Layout Techniques course (RFLT). Analog Layout Techniques course and Analog Layout, Advanced Techniques course. http://www.icmaskdesign.com/master-ic-training/training-courses/