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March 2006

IC Mask Design Sets New Unprecedented Standard With EDA Toolset Offering

IC Mask Design is now offering a unique and compelling alternative to the relentless trade-off between EDA Tool costs and Engineering Labour costs.

We have successfully negotiated a deal with a leading EDA vendor that will enable us to provide a complete Physical Design Services outsourcing option with:

The following sample estimate illustrates the immediate benefits and the associated cost of engaging IC Mask Design.

Sample Design

Process 130nm
Gate Count 3 million
Clock Speed 200MHz
No. of RAM Instances 50
Macro Blocks Single PLL
Estimated Die Size 8mm x 8mm

Cost Estimate

Services Included Price

Floorplanning, place & route, clock tree synthesis, static timing analysis, timing closure and physical verification   €250,000
Experienced Place & Route Engineer €0.00
Program Manager €0.00
Total Estimated Cost €250,000

Confidentiality

The initial step in any engagement would be the signing of an NDA.

Security

In early 2005, IC Mask Design successfully fulfilled the requirements of an extensive audit, conducted by a major semiconductor organisation.

The focus of this audit was on both the ‘Physical Security’ and ‘IT Infrastructural Security’ of our Design Centre in Ireland.

Details of this documentation is available upon request.

Engineering Expertise

IC Mask Design has a professional global team of industry leading IC Layout Engineers. Our engineers have worked on leading edge designs down to 65nm, and have taped out using Magma, Cadence, Synopsys and Mentor Toolsets.

Details of sample projects are furnished upon request.

*Note: If a cost estimation based on a particular design requirement is preferred, IC Mask Design would be delighted to review this design, and provide an appropriate estimation.




About IC Mask Design

IC Mask Design is an industry leader in the provision of Physical Design Services and Software Solutions to the semiconductor industry. The company’s services encompass IC Layout and Training Programs, delivering expertise in Analog, RF, mixed-signal and digital design using the latest tools from leading EDA vendors. IC Mask Design also provides training courses covering the complete spectrum of physical design. Its Analog Layout Acceleration Platform aims to dramatically reduce analog layout design cycle time whilst producing optimal quality layout structures which incorporate circuit functionality requirements and process artefacts.

Further information is available from IC Mask Design's web site.

For more details, please contact:

Fergal Brosnan
Tel: +353 (0)61 448 530
Email: