| Layout Techniques for ESD Structures |
LTESD01 |
Discusses the issues involved in the physical design of circuits used in the protection of ESD on-chip. |
| Layout Parasitics |
LPAR01 |
Discusses how parasitics occur in layout during fabrication. Introduces how extraction tools calculate the values of these parasitic devices and discusses typical parasitic extraction and back annotation flow |
| Layout Techniques for Improved Yield in Silicon |
LYLD01 |
Typical yield issues involved in deep sub-micron processes and layout techniques used to increase yield. Includes issues such as shallow trench isolation stress, antenna affect, electromigration etc. |
| Layout Noise Isolation |
LNOI01 |
Layout techniques used on-chip to improve noise isolation and reduce on-chip noise. |
| High Power MOS layout |
HPMLP01 |
Techniques used to layout MOS high-power transistors. |
| Skill Programming for the Physical Designer |
SKLP01 |
Cadence SKILL programming aimed at the physical design engineer. Focuses on developing code which can automate many of the physical design tasks. |
| Understanding & Improving Device Parasitics |
DVCP01 |
Examines the components used in analog IC design. The course covers the physical makeup/layout of these devices as well as the device parasitics associated with each. Techniques for reducing these parasitics are discussed. |
| Developing and Implementing a Layout Flow |
LFLW01 |
Introduction of a layout flow in which the quality of the layouts can be checked, guaranteeing repeatable high quality designs across projects. |
