Layout Acceleration Platform - Product Features
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| Feature | Specification | Benefit |
| Accelerates Analog Physical Layout | Automatically generates individual devices and structures e.g. MOS, current mirrors, differential pairs and resistor dividers | Accelerates full custom analog layout process, improving overall productivity and faster time to market |
| Parasitic Aware | Considers device and interconnect parasitics during generation | Produces optimal solution based on user parasitic requirements |
| Ensures Quality & Consistency of physical design | Automatically generates devices and structures that are “silicon-aware” with the intelligence to contextually tune for specific layouts | Ensures consistent high quality and guarantees design standards are the same for different designers and projects across the whole organisation |
| Guarantees Matching | Applies matching techniques to address a number of common processing artefacts. These include:
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Ensures processing effects are reduced or applied equally across all matched devices |
| Layout Optimisation to Improve Yield | Produces devices and structure that are optimised for yield, including double contacts/vias and support for DFM (Design for Manufacture) rules | Improves yield in layout |
| Easy to use - based on Design Rule Inputs | Accepts manufacturing design rules as an input, for new and existing technology nodes | No change to design methodology. Ensures devices and structures scale with design rules |
| Functionally Aware | Understands the key functional differences between various structures within the circuit | Ensures the generation is targeted towards creating the optimal design primitives possible |
| User Tuning / Customisation | Offers the user the ability to prioritize parasitic performance over matching requirements (and vice versa) and prioritize key matching concerns over others within a circuit | Ensures the output meets specific matching, parasitic and performance requirements for the overall design |
| Quick Floor Plan Size Estimation | Its in-built intelligence to be silicon and functionally aware allows users to quickly select and tweak devices and structures and accurately estimate the physical design size | Allows users to quickly and accurately estimate the size of the floor plan in advance of the layout task, saving time and unnecessary iterations |