IC Layout Acceleration Platform
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IC Mask Design has developed an IC Layout Acceleration Platform which significantly accelerates the full custom analog layout process through the generation of devices and common analog structures, revolutionizing the entire layout process.
The platform is silicon aware, with a focus on matching, parasitic performance and design for manufacturability. It produces the optimal solution through a simple and concise setup that requires only manufacturing design rules for new and existing technology nodes as input. It also ensures a consistent high quality and guarantees design standards are the same for different designers and projects across the whole organization.
It has been recognised by customers and foundries to significantly accelerate the IC design process, lower design costs, decrease risk and ultimately reduce their time to market.
Tanner EDA, a leading tool provider for the design, layout and verification of analog and mixed-signal ICs, recognises the value of IC Mask Design’s patented layout acceleration platform. They are exclusively licensing the technology and have integrated it into their custom IC L-Edit layout editor design suite.
Availability/Contact
Tanner EDA currently offers this breakthrough toolset based on IC Mask Design’s proprietary technology.
For worldwide sales contacts visit http://www.tannereda.com/