The Impact of Dishing on Copper Tracks
Vadym Skyba of IC Mask examines how to calculate and mitigate this consequence of over-polishing
Chemical-Mechanical Polishing, or CMP, is used to erode excess deposited materials, such as SiO2 (dielectric), Cu (copper) or Tungsten (contacts) from the silicon wafers during the manufacturing process. Each of these materials has different hardness, and the CMP process has to be adjusted for each one in terms of applied pressure and the chemistry of the liquid (slurry) used to coat the polishing pad.
With copper, prolonged polishing may be required to make sure all excess metal particles have been removed, which means the pad may be going over dielectric as well as copper at the same time. Since copper is softer than the dielectric, it erodes quicker, and because of this, over-polishing leads to dishing of the copper surface.
Metal dishing as a result of over-polishing.
This reduces the height, or thickness, of the metal track. From looking at the formula used to calculate resistance of a piece of conductive material, we can see that reducing thickness (T) will make the denominator smaller, which means the value for resistance will become larger. In short, dishing increases the resistance of a metal track.
In extreme cases, dishing, as well as erosion, another side-effect of over-polishing, may even lead to open connections in the chip.
Experiments carried out in 2001 for the Massachusetts Institute of Technology1 looked at the effects of over-polishing, particularly dishing of copper tracks and the dielectric. The results showed that copper tracks with widths from 0.5um to 2um suffered 20-30nm of dishing. More interestingly, dishing of tracks with widths of up to 25um leveled off after a short period. Dishing of wider tracks increased with the polishing duration and did not get to a constant level, reaching around 450nm after 3 minutes of over-polishing.
Another point of interest in that study was made in regards to the spacing between tracks. Copper tracks with a pitch of 2-3um received less than 30nm of dishing, where more isolated tracks with a pitch of 200um received close to 200nm.
A precise mathematical analysis of the amount of dishing is very difficult due the number of variables present at submicron levels, such as the abrasive particle diameter, pad surface roughness and particle distribution. However a simple mathematical formula could be derived to help demonstrate the impact of dishing. As an example, we will compare the use of a single wide track to using two smaller tracks. The total width of the two smaller tracks is equal to the width of the wide track, so that if no dishing occurred, the total resistance in both cases should be the same. With dishing, the thickness of the wide track is Tx, the thickness of the smaller tracks is Ty, and the difference between them is Δ. Similarly, we will use Rx and Ry to refer to the corresponding resistance values. As was already mentioned, thinner tracks receive less dishing, so the relationship between the two thicknesses is Tx = Ty – Δ.
Using a wide metal track vs using two tracks of smaller width.
Using the formula for calculating resistance, which was mentioned earlier we can state the following:
It is now easy to conclude that the bigger Δ is, the smaller Ry becomes in relation to Rx.
To reduce dishing, and erosion, of metal tracks, it is recommended to reduce density variation on the chip, which is why we have minimum and maximum density rules. Filling blank areas with dummy metal helps improve uniformity. Another known way to reduce the effects of dishing is to use multiple, thinner metal tracks instead of a single wide track. When thinner tracks are used, the copper is being protected by the adjacent dielectric material. As this erodes much more slowly, the pad cannot reach far into the small trenches. When the track is wide, however, the polishing pad can easily dished copper surface.
- J.-Y. Lai, N. Saka, and J. H. Chun, J. Electrochem. Soc., 149, G41 (2002).
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