IC Mask Design to Hold Very Deep Submicron Layout Course in Munich Oct 17th-18th

Due to increased demand in the region, IC Mask Design will hold their next Very Deep Submicron Layout course in Munich. Running from Oct 17th to Oct 18th the VDSM course is targeted at candidates who wish to develop the skills necessary to understand the challenges faced by physical engineers in completing layouts at deep submicron levels and provides practical real- life solutions.  This approach enables the instructor to deliver explanations and advice at an appropriate level of detail and ensures training covers all operating issues relating to the candidate’s particular background. Companies already attending are involved in sensor, contactless security, RF & Wireless Control and Connectivity Applications.

Course Code


Course Pre-requisite

Prior experience of analog layout on a CMOS process.

Learning Outcomes

  • Layout of VDSL circuits on CMOS processes
  • Understanding the impact layout has on yield and discuss how yield is no longer just a foundry responsibility
  • Understanding the parasitics elements introduced by the VDSL process

Syllabus Content

  • CMOS Scaling Implications
  • Yield
  • Interconnect Parasitics
  • Device Parasitics
  • Matching
  • Isolation Strategies
  • Design for Manufacture

To download an Acrobat PDF version of the course syllabus, please click here.

To download the IC Mask Design Training & Corporate brochure click here.