Course: Very Deep Submicron Layout (VDSL)
The VDSL course is targeted towards developing the skills necessary to understand the challanges faced by physical engineers in completing layouts at deep submicron levels and provides practical real life solutions. |
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Course Code
VDSL01
Course Prerequisite
Prior experience of analog layout on a CMOS process
Learning Outcomes
- Layout of VDSL circuits on CMOS processes
- Understanding the impact layout has on yield and discuss how yield is no longer just a foundry responsibility
- Understanding the parasitics elements introduced by the VDSL process
Syllabus Content
- CMOS Scaling Implications
- Yield
- Interconnect Parasitics
- Device Parasitics
- Matching
- Isolation Strategies
- Design for Manufacture
To download an Acrobat pdf version of the course syllabus, please right click the link below and choose "Save As"
VDSL01 Course SyllabusTo download an Acrobat pdf version of our training brochure, please right click the link below and choose "Save As"