Course: High Voltage Layout
Supplies used in today's ICs vary from about 1V to more than 100V, depending on the technology and the application (flat panel displays, robotics automobile etc.). Also with the advance in shrinking technology nodes and low-power technologies, core voltages are decreasing whilst the interfaces still need to be at the likes of 5V. This high voltage course addresses the key physical design challenges associated with these issues. |
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Course Code
HVLT01
Course Prerequisite
Experience of analog layout on a CMOS process.
Learning Outcomes
- Knowledgeable of high voltage devices on CMOS processes
- Layout for HV power design
- ESD layout in HV design
- Knowledge of metal routing schemes
Syllabus Content
- CMOS fundamentals
- Overview of how CMOS devices are fabricated - HV CMOS definition and layout requirements
- Implications on layout using high operating voltage devices
- Techniques to allow high voltage operation
- Different operating levels on one die
- HV layout for power design - ESD protection for HV designs
- Protecting the HV devices from the outside world - EMI proofing
- Methods of reducing the effects of EMI on other circuits - Electromigration and metal routing strategies
- Layout techniques for improving electromigration resistance and reducing stresses in high current paths
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HVLT01 Course SyllabusTo download an Acrobat pdf version of our training brochure, please right click the link below and choose "Save As"