Course: Layout for ESD
This course focuses on the layout of devices used in ESD protection schemes for ICs. Content includes device compositions, parasitic effects of ESD structures, isolation schemes, and whole chip ESD protection methodologies. |
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Course Code
ESDLT01
Course Prerequisite
None.
Learning Outcomes
- A basic understanding of ESD Protection methodologies
- Understanding the parasitic elements introduced by ESD structures
- Understanding the layout of ESD protection devices
Syllabus Content
- ESD Defined
- Introduction to ESD
- ESD protection schemes
- ESD related failures
- CMOS Technology Review
- Diode ESD protection device
- Resistor ESD protection device
- MOS ESD protection device
- Ground/Power Strategies
- Design Rules specific to ESD
- Electromigration issues (i.e. spacings, thickness, uniform current densities, etc.)
- RF/Mixed Signal ESD Protection Schemes
- Parasitic effects of ESD protection structures
- Noise Isolation
- Whole Chip ESD Protection Schemes
- Input ESD Protection Schemes
- Output ESD Protection Schemes
- Power Clamps
- Multiple domains
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ESDLT01 Course SyllabusTo download an Acrobat pdf version of our training brochure, please right click the link below and choose "Save As"