IC Mask Design: The Experts In All Aspects of IC Layout
IC Layout
Acceleration Platform
- Accelerates analog layout
- Easy-to-use based on standard design rule inputs
- No change in design methodology
- Considers parasitics, guarantees matching
- Ensures quality and consistency across all users
IC Layout
Services
- Experience working
with tier 1, tier 2, multinational and
fabless companies worldwide - Experts in a wide range of foundries, VDSM technologies and processes e.g. RFCMOS
- Project management service includes expert advice and guidance
IC Layout
Training
- Industry recognized experts in IC layout training
- Methodology training independent of EDA environment
- Up-to-date material incorporating latest technology nodes
- Standard and customized training courses available
IC Layout Services
Master-IC Training™
- Layout for ESD »
- Introduction to CMOS Layout »
- Analog Layout Techniques »
- Analog Layout Advanced Techniques »
- RF Layout »
- Custom Digital Layout Techniques »
- Standard Cell Place & Route »
- Timing Closure in the Backend Design Flow »
- Very Deep Submicron Layout »
- Block Level Layout (Bandgap / PLL / ADC / DAC) »
Latest News
Visit us at ChipEx 2013, May 1st at the David Intercontinental Hotel Tel-Aviv www.chipex.co.il.
For more details, contact Adi Katav on akatav@kaltech.co.il
NMI Conference Presentation »
Download IC Mask Design's “New Technology Nodes” presentation given at the NMI Conference.