IC Mask Design: The Experts In All Aspects of IC Layout

IC Layout
Acceleration Platform

  • Accelerates analog layout
  • Easy-to-use based on standard design rule inputs
  • No change in design methodology
  • Considers parasitics, guarantees matching
  • Ensures quality and consistency across all users

IC Layout
Services

  • Experience working
    with tier 1, tier 2, multinational and
    fabless companies worldwide
  • Experts in a wide range of foundries, VDSM technologies and processes e.g. RFCMOS
  • Project management service includes expert advice and guidance

IC Layout
Training

  • Industry recognized experts in IC layout training
  • Methodology training independent of EDA environment
  • Up-to-date material incorporating latest technology nodes
  • Standard and customized training courses available

IC Layout Services

 

Master-IC Training™

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Latest News

European Expert Panel Proposes New Analogue IC Design Methodology to Counter the Analogue Bottleneck » GSA, the voice of the global semiconductor industry, recently hosted a panel of European analogue IC design experts at the GSA & IET International Semiconductor Forum in London on 19 May. The discussion led to a possible solution to the analogue IC design bottleneck.
IC Mask Design to Present at the Design Automation Conference in Anaheim California » Chief Technical Officer Ciaran Whyte to present HiPerDevGen, a High Performance Device and Structure Generation Platform for A/MS Design IC Mask Design to Participate on Panel Discussion at GSA / IET Semiconductor Forum » Chief Technical Officer Ciaran Whyte to present his views on Analog: The New Bottleneck IC Mask Design Completes Physical Design of Video Processor IC on 65nm Technology Node » IC Mask Design has responsibility for Digital Physical Implementation Layout Acceleration Platform Whitepaper » Now available to download.